This application relates to methods and apparatus for reduction of charge collection in semiconductor processing; and more particularly relates to the reduction of damage caused by process-induced charge collection in cell based arrays.
It has become well known that certain processes used in semiconductor fabrication can induce collection of charge in some polysilicon or metal structures during the fabrication of a semiconductor device. More specifically, use of a plasma ambient during processing has been shown to induce charge in polysilicon or metal structures sometimes referred to as xe2x80x9cantennaxe2x80x9d or xe2x80x9ccharge collectorxe2x80x9d structures. This collection of charge has been shown capable of causing damage to thin gate oxides in at least some instances, and thus to reduce yield significantly. The problem is exacerbated as critical device dimensions are reduced, for example one-quarter m, with the concomitant reduction in the thickness of gate oxides to, for example, ten nm or less, and in at least some instances on the order of seven nanometers.
The damage possible from such processing steps has been described in the literature. One article, entitled xe2x80x9cPlasma-Parameter Dependence of Thin-Oxide Damage from Wafer Charging During Electron-Cyclotron-Resonance Plasma Processingxe2x80x9d is found in the February 1997 issue of IEEE Transactions on Semiconductor Manufacturing, Vol. 10, No. 1, p. 154. A related article, entitled xe2x80x9cPlasma Etching Charge-Up Damage to Thin Oxides,xe2x80x9d can be found in the August 1993 issue of Solid State Technology, at page 29. Both articles make clear that process-induced present significant risks to yields.
Although the adverse results due to the antenna effect are well known in the current art, it is much less certain how best to counteract the problem. Although a diode has been mentioned abstractly in the literature, no successful implementation has been demonstrated. More particularly, the implementation of a diode has heretofore involved significant loss of area. This loss of area makes implementation of a diode substantially less desirable, since die area is critical to modern complex designs.
There has therefore been a need to develop a circuit design which minimizes or eliminates the antenna effect while at the same time minimizing the amount of area lost.
The present invention substantially overcomes the limitations of the prior art by providing an extremely compact structure which dissipates charge collected during processing tips of semiconductor structures. The present invention is particularly suited to cell-based arrays, although it is also suited to other semiconductor devices.
In particular, the present invention involves modification of the fabrication process to include providing a means for discharging the charge-collection structures identified in the prior art, while at the same time minimizing the amount of die area needed to achieve such results. More specifically, for a substrate of a first type, an area of a second type is deposited in a location suitable for connection to a charge collection structure to be fabricated in subsequent steps. The charge collector structure may be, for example, a polysilicon or metal run connected to a first gate and intended ultimately to connect to other structures, but left unconnected for a portion of the processing steps.
The combination of a substrate of a first type and a deposition area of a second type can be seen to create a diode. By positioning the diode in close proximity to the charge collector structure, the two structures may be connected by means of any of a plurality of local interconnect techniques. The diode permits charge to be dissipated during processing, but essentially has negligible effect on the operation of the finally-constructed circuit. In this way the antenna effect is minimized or eliminated, and yield is improved.
In a presently preferred embodiment, the diode of the present invention is placed in a location which will eventually be a connecting pad. In this manner, substantially the entire die area may be utilized for semiconductor structures implementing the overall circuit, while at the same time eliminating the antenna effect. The invention is particularly well-suited to complex integrated circuits such as cell-based arrays, but may be successfully implemented in a wide variety of circuit designs.
The present invention will be better understood from the following Detailed Description of the Invention, taken together with the appended drawings. Although the invention is explained in the context of a cell-based array, it is to be understood that such an embodiment is exemplary only and not limiting.